Two basic data receiver architectures are prevalent in the communications and computer industries today: tracking receivers and oversampling receivers.
Tracking Receivers
In brief, a tracking receiver employs a phase locked-loop (PLL) based architecture that in operation, compares the phase of received data with a local clock phase and modulates the frequency of the local clock to correspond with the frequency and phase of the incoming data. A tracking receiver therefore tracks the frequency of the received data so that the tracking can reliably receive the data. By tracking the frequency of the received data, the receiver can tolerate phase and amplitude jitter that may be present in the received waveform due to multiple noise sources. An alternate implementation of a tracking receiver employs a delayed-lock loop (DLL), which serves a similar function as the PLL.
Oversampling Receiver
An oversampling receiver does not require a PLL or DLL but instead operates by obtaining a series of samples of the received data and filtering out noise based on the history of the sampled data. The samples taken by an oversampling receiver are at a frequency that is some multiple (e.g., three times) of the nominal frequency (i.e., without phase and amplitude jitter) of the received data. By taking so many samples of the received data, the transmitted signal can be determined without having to modulate the clock frequency of the receiver.
Both tracking and oversampling receivers have some drawbacks. Tracking receivers require analog circuits that are sensitive to noise. Often the designs of tracking receivers are large and/or need additional power to function correctly in integrated circuits that contain a large amount of high frequency digital logic circuitry, such as a microprocessor, memory controller or I/O (input/output) bridge. Extreme care must be taken when laying out a circuit board for a receiver that includes very sensitive analog circuits (i.e. a phase-locked loop circuit) and very high speed digital logic, which draws down the voltage rails very quickly, causing large noise sources. Consequently circuit designers employ various techniques to lessen the impact of these noise sources on the sensitive analog circuits. These techniques however, often result in increased circuit costs (both in size and investment).
In general, over-sampling receivers contain a much higher percentage of digital circuitry than tracking receivers, and therefore should be more tolerant of noise sources. However, the rate at which over-sampling receivers sample the incoming waveform introduces an additional source of jitter, often called quantization jitter, which reduces the noise budget in the transceiver/channel subsystem. As the rate of oversampling is at least three times the data rate, the speed of the digital logic limits the overall speed of the communication process to a much lower rate than otherwise possible using a tracking receiver. Consequently, very high-speed receivers employ PLL circuits to enable operation of the receiver at a level much nearer to the limit of the digital circuitry, than that which could be accomplished with oversampling.
The invention is therefore directed to the problem of developing a digital receiver that can operate at the speed of the digital circuitry, yet does not require sensitive analog circuits.